Many Static Read-Only Memory (SRAM) designs provide high read/write speeds and low power consumption. SRAM is therefore particularly suited for implementation as a microprocessor cache. However, shrinking dimensions of transistors used to implement SRAM and variability in a number and location of their channel dopant atoms may result in problematic variations in the transistors"" threshold voltages.
These variations may reduce the stability of an SRAM cell during a read operation. In this regard, SRAM stability generally refers to a probability that an SRAM cell will flip its content during a read operation. FIG. 1 illustrates a conventional SRAM architecture for use in describing this phenomenon.
More particularly, architecture 1 comprises a portion of one column of a conventional SRAM block. Architecture 1 includes memory cells 10, 11 and 12, as well as other unshown memory cells disposed between memory cells 11 and 12. Each memory cell is coupled to bit-line BL and to complementary bit-line BL#. Each memory cell is also coupled to a respective one of word-lines WL1, WL2 and WLN, which provide a signal to allow read or write access to a respective memory cell.
Bit-line BL and complementary bit-line BL# are each coupled to pre-charge circuit 20. Pre-charge circuit 20 includes p-channel metal oxide semiconductor (PMOS) transistors 21 through 23. A source terminal of each of PMOS transistors 21 and 22 is coupled to a supply voltage (Vcc), and a gate terminal of each of transistors 21 and 22 is coupled to a pre-charge (PCH) signal line. A drain terminal of PMOS transistor 21 is coupled to bit-line BL and a drain terminal of PMOS transistor 22 is coupled to complementary bit-line BL#. Lastly, a gate terminal of PMOS transistor 23 is also coupled to the PCH signal line, with either one of a drain and/or a source of PMOS transistor 23 coupled to one of bit-line BL and complementary bit-line BL#.
Pre-charge circuit 20 operates to charge bit-line BL and complementary bit-line BL# to in response to the PCH signal. In a case that the PCH signal is enabled (active low), transistors 21 and 22 electrically connect bit-line BL and complementary bit-line BL# to the supply voltage. Additionally, transistor 23 connects bit-line BL and complementary bit-line BL# to equalize the potentials thereof.
To read a value stored in a memory cell, a word-line associated with the memory cell is enabled after the bit-lines BL and BL# have been pre-charged. Sense amplifiers coupled to the bit-lines then monitor a difference between voltages on the bit-lines to determine the stored value. FIG. 2 is a detailed view of a conventional six-transistor (6T) SRAM memory for purposes of explaining the read operation and the problem of cell instability.
FIG. 2 shows elements of SRAM memory cell 10. Nodes 30 and 31 provide complementary bit values by virtue of the illustrated architecture. According to convention, the bit value at node 30 is considered to be the value stored by cell 10.
Memory cell 10 includes pull-up PMOS transistors 32 and 33, as well as pull-down n-channel metal oxide semiconductor (NMOS) transistors 34 and 35. Cell 10 also includes NMOS access transistor 36, which is coupled to bit-line BL and to node 30. NMOS access transistor 37 is similarly coupled to complementary bit-line BL# and to node 31. A gate terminal of each of access transistors 36 and 37 is coupled to word-line WL1. Accordingly, enabling word-line WL1 (active high) electrically connects bit-line BL to node 30 and complementary bit-line BL# to node 31.
The foregoing description of a read operation will assume that a bit value at node 30 is xe2x80x9c1xe2x80x9d (V30 Vcc) and a bit value at node 31 is xe2x80x9c0xe2x80x9d (V31 0). Consequently, transistor 32 is turned on and transistor 34 is turned off by the voltage at node 31, thereby holding the voltage at node 30 to Vcc. Similarly, the voltage at node 30 turns off transistor 33 and turns on transistor 35, thereby coupling node 31 to ground.
At the beginning of a read operation, bit-lines BL and BL# are pre-charged to the supply voltage by enabling the PCH signal. The PCH signal is disabled and the word-line WL1 signal is enabled to electrically connect bit-line BL to node 30 and complementary bit-line BL# to node 31. Since both bit-line BL and node 30 were charged to the supply voltage prior to enabling the word-line WL1 signal, the voltage on bit-line BL remains substantially unchanged. However, the voltage on bit-line BL will dip due to its direct path through transistors 37 and 35 to ground. The aforementioned sense amplifiers coupled to the column of FIG. 1 sense the resulting difference between the voltages on bit-line BL and complementary bit-line BL# in order to determine that memory cell 10 stores a bit value of xe2x80x9c1xe2x80x9d.
As the voltage on complementary bit-line BL# dips below the supply voltage, the voltage at node 31 will rise above ground due to the voltage divider composed of transistors 37 and 35. In some scenarios, the voltage at node 31 may rise to a level that causes cell 10 to xe2x80x9cflipxe2x80x9d its value and store a xe2x80x9c0xe2x80x9d rather than a xe2x80x9c1xe2x80x9d. Such a result should not be caused by a read operation, and is conventionally addressed by lowering the resistance of transistor 35 with respect to the resistance of transistor 37.
It has been proposed to lower the relative resistances by increasing the width of the pull-down NMOS transistors, which increases the size of the memory cell. Other proposals increase the length of the access transistors, which decreases the speed at which the memory cell can be read. More complex approaches increase the strength of the pull-down transistors by driving their source terminals to a negative voltage while or before the word-line signal is enabled, or reduce the strength of the access transistors by pre-charging the bit-lines to a voltage that is slightly lower than the supply voltage. Both of these latter approaches require additional voltage sources and corresponding area and power overhead.